There is a photograph from Friday's Tokyo signing that deserves more attention than the communiqué: the Japanese consortium's chief engineer, mid-conversation with two young Indian process engineers, all three ignoring the ministers behind them. That conversation — not the ¥2.1 trillion headline — is where India's semiconductor decade will be decided.
The corridor framework is genuinely well-designed, and I say that as someone professionally obligated to doubt frameworks. It pairs complements rather than rivals: Japanese equipment, materials and process discipline with Indian engineering scale and market growth. It names real nodes — Dholera's analog fab, Jagiroad's packaging cluster, Kochi's power-electronics design centre — rather than gesturing at ecosystems. And its supply-assurance annexe quietly does something India has never had: a treaty-grade claim on chip supply during a crisis.
Why analog-first is the right unfashionable bet
Critics note that 40-nanometre analog is two decades behind the leading edge, and they are right in the way that misses the point. The leading edge is a three-company oligopoly defended by capital costs that would consume India's entire programme on a single fab. The 28-to-65-nanometre band, meanwhile, is where power electronics, automotive controllers, telecom infrastructure and defence systems actually live — the chips whose absence stopped Indian car lines in 2021, not the ones in flagship phones.
Japan's own history argues for the sequence. It built materials and equipment dominance — the unglamorous layers where it still holds pricing power — before and after its memory empire rose and fell. India copying Japan's supply-chain position rather than Taiwan's fab position is strategy, not timidity.
The binding constraint wears a bunny suit
Here is the number that should worry the programme's champions: 1,100. That is the process-engineering headcount Dholera's consortium needs on site by March for the fab's qualification runs. India produces world-class chip designers by the thousand — design is software-adjacent, and we are good at software-adjacent. Process engineering is different: it is chemistry, vacuum physics and statistical discipline practised at 3 a.m. in a cleanroom, and the country's entire experienced pool is smaller than one Taiwanese fab's night shift.
The framework's twelve funded M.Tech programmes are the right instrument on the wrong timeline; their first graduates arrive in 2028. The bridge must be built from returnees — the Indian process engineers currently running fabs in Hsinchu, Dresden and Phoenix — and the programme has been slower than it should be to treat them as strategic assets, with the salary structures, equity and lab autonomy that would bring them home.
Capital is committed. The partner is right. The geopolitics have aligned with a clarity that will not recur. What remains is the oldest constraint in industrial history: people who know how. The next twelve months tell us whether we solved it.
Adarsh Ashok is Technology and Defence Correspondent at LoktantraVani.